Tuesday, June 12, 2012

The Set-Reset Latch

Set-Reset Introduction

The Set-Reset latch (SR-latch) is composed of 2 NOR gates that feed their output back into the one of the others inputs. The NOR gated are said to be cross-coupled. See the picture to the left.

It's Beautiful on the Outside..

The SR latch seems perfect at first glance; however, the set-reset latch has a one fatal flaw: an unpredictable state. Most likely, if you try to think about the design for too long you will end up with a headache because the resulting Q and Q' during R=1 S=1 are opposite, and unpredictable.

As a result of that problem more complex designs for the latch were designed, such as the Set-Reset Gate that includes a clock in its design. A clock determines when input can be processed.

This is the logic diagram for S'R' Latch. The S'R' latch is constructed from 2 cross-coupled NAND gates and is commonly confused with the SR Latch.
Set-Reset Latch
S R Q Q' Description
0 0 Q Q' No change in Q and Q'
0 1 0 1 Clear Q
1 0 1 0 Set Q
1 1 ? ? Undesirable state

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